The present invention relates to a semiconductor device, and, more particularly, to a technique which is effective in achieving a reduction in the size of a module, such as a power amplifier module.
As a structure for achieving a reduction in the size of a semiconductor device, there is a known SCP (Stacked Chips Package) structure in which semiconductor chips are arranged in a superimposed fashion. In the SCP structure, a lower-layer chip is provided, and an upper-layer chip that is smaller than the lower-layer chip is superimposed on the lower-layer chip. Thus, the chips are stacked in two stages so as to attain a reduction in size (see, for example, Patent Literature 1).
Patent Literature 1:                Japanese Patent Publication Laid-Open No. Hei 7(1995)-58280 (page 3, FIG. 2)        